1. Field of the Invention
The present invention relates to a process for producing a semiconductor device having HSGs suitable for an electrode of a capacitor, and in particular to a process for producing a semiconductor device having HSGs wherein variation in the size of the HSGs is restrained.
2. Description of the Related Art
Recently, in semiconductor devices such as a semiconductor memory, for example, dynamic RAM (DRAM), a far higher integration degree has been required than in the past. In order to respond to this requirement, areas necessary for respective memory cells have been remarkably reduced. For example, in the case of 1 M DRAM or 4M DRAM, such a design rule is adopted that a minimum design width will be 0.8 .mu.m. In the case of 16 M DRAM, such a design rule is adopted that a minimum design width will be 0.6 .mu.m or less. On the contrary, when the areas for the memory cells are reduced, the quantity of charges which can be accumulated in the memory cells is also reduced. Thus, as the integration degree becomes higher, it becomes more difficult to ensure the quantity of charges necessary for the memory cells.
For this reason, memory cells having a trenched or stacked capacitor are proposed and made practicable to ensure the quantity of charges necessary for the memory cells.
Resistance to soft errors of the memory cell having a stack-type capacitor is higher than that of the memory cell having a trench-type capacitor. The memory cell having a stack-type capacitor has a structure which provides less damages to a silicon substrate than the memory cell having a trench-type capacitor. Thus, the memory cell having a stack-type capacitor is expected as a memory cell in the future.
By making the trench-type capacitor into a stack-type-trenched structure, improvement in resistance to .alpha.-rays of the trench has been investigated. Therefore, the stack-type memory cell is promising as a next generation technique.
As stack-type capacitors which can be applied to DRAM having a capacitance of 64 M or more, ones using hemispherical-grain (HSG) technique has been proposed. In the HSG technique, many hemispherical grains or mushroom-like grains are formed on the surface of accumulating electrodes of the capacitor so that the surface area of the accumulating electrodes is substantially enlarged. Thus, a large capacitance can be ensured.
For example, Japanese Patent Application Laid-Open No. 3-272165 discloses a process for producing an accumulating electrode having hemispherical grains. In this prior art, hemispherical grains are formed at a temperature where a silicon film is transited from an amorphous state to a polycrystal state, in the step of growing the silicon film by LPCVD. This silicon film is applied to the lower electrode of a stack-type capacitor. Thus, the surface area of the electrode is remarkably enlarged so that the quantity of accumulated charges is increased.
Japanese Patent Application Laid-Open No. 3-263370 states that in the step of growing a silicon film by LPCVD the surface area of an electrode, which has a surface whose rough state is unclear, increases at a temperature where the silicon film is transited from an amorphous state to a polycrystal state.
An article published thereafter "Device application and structure observation for hemispherical grained Si" Journal of Applied Physics, Vol. 71, No 7, pp. 3538-3543, 1992 by Watanabe et al. made the growing mechanism of hemispherical or mushroom-like grains evident.
According to this article, grains constituting roughness of the Si surface are not formed in the step of growing the silicon film by CVD, but are formed as follows. Crystal nuclei are thermally formed in an annealing step immediately after the silicon film is grown, and then silicon atoms migrating on the Si surface are captured by the crystal nuclei so that the grains constituting roughness of the Si surface are formed.
These publication and article state that in order to form roughness on the surface of the electrode it is important to control temperature into a very narrow temperature range within which amorphous silicon is transited into polycrystal silicon.
The prior art process for producing a stack-type capacitor wherein the surface of its electrode has roughness will be described. An interlayer insulation film is first formed on a semiconductor substrate having semiconductor elements such as MOSFET. At a given position of this interlayer insulation film a contact hole is formed and then a silicon film which will finally electrically connected to semiconductor elements through the contact hole is deposited. Subsequently, this silicon film is patterned to form a lower electrode. At this time, roughness is produced on the surface of the lower electrode by, e.g., the aforementioned prior art. After that, a capacitive insulator film and an upper electrode are formed successively to obtain a stack-type capacitor.
As described above, it is reported that hemispherical or mushroom-like grains, which constitute roughness, can be formed within a very narrow transiting temperature range where the deposited silicon film is transited from an amorphous state to a polycrystal state.
However, when the temperature inside a furnace is accurately set into the temperature at which amorphous silicon is transited to polycrystal silicon, which is described in Japanese Patent Application Laid-Open No. 3-272165 and then roughness is attempted to be formed on the surfaces of many wafers at a time by using LPCVD apparatus, a problem is caused that properties of devices are varied dependently on the respective positions of the wafers inside the furnace.
When an LPCVD apparatus for batch process having a normal furnace tube is used to deposit a silicon film, the temperature at the downstream side of ingredient gas flow is generally higher than that at the upstream side of the ingredient gas flow in order to improve uniformity of the silicon film thickness inside the furnace.
This is because, in the film depositing apparatus for batch process, film-forming ingredient gas is consumed to form a film when the gas flows in the furnace, and consequently the concentration of the ingredient gas drops at the downstream side of the gas flow. In other words, if the temperature inside the reaction furnace is made uniform, the thickness of the film at the upstream side of the gas flow becomes larger than that of the film at the downstream side because of difference in the concentration of the ingredient gas. Thus, the temperature at the downstream side of the gas flow, at which the concentration of the ingredient gas is liable to be low, is raised so that film-forming efficiency is improved at the downstream side to make the thickness of the film uniform.
However, when the temperature at the downstream side of the ingredient gas flow is set to a somewhat higher value than that at the upstream side in the process of forming roughness on the surfaces of many wafers at a time, the uniformity of the film thickness is improved but the uniformity of the roughness is deteriorated to a considerably degree.
When the temperature inside a furnace is made uniform and an LPCVD apparatus is used so as to form HSGs in a great number of wafers in such a manner as above, a size, a density and a shape of the grains are varied dependently on the respective positions of the wafers inside the furnace. The difference in the surface shape of the wafers causes the quantity of charges which are to be accumulated in capacitors to be varied dependently on the respective positions of the wafers inside the furnace when they are treated in the LPCVD apparatus. Furthermore, when the temperature at the downstream side of the ingredient gas flow is higher than that at the upstream side thereof, the uniformity of the film thickness is improved but the state of the formed roughness is deteriorated. In short, in the prior art process for producing a semiconductor device it is very difficult to form roughness having a uniform shape independent on the positions of wafers inside a furnace on the surface of a silicon film.